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Mocana NanoSSH - Embedded SSH Client and Server

vendor    

eXsultation (Training Company)
The ASIC and FPGA designers' choice for VHDL, Verilog and HDL related training. We deliver dynamic training services right to your doorstep. Advanced Verification and Design Training Using a variety of EDA tools and operating environments, our teaching staff has the expertise to bring your ASIC and FPGA teams up to speed with the ever growing complexity of today's designs.
preview: http://www.exsultation.com  

newsgroup    

VLSI Discussion Site
Newsgroup postings and discussions on soc, circuits and other chip design issues.
preview: http://www.vlsibank.com  

archive    

Semico Asic Studies (Paid Research)
SoC Design Cost Analysis: Perspectives on Critical Issues ASIC Market Analysis - July 2007 ASIC Market Forecast and Analysis: Slower Growth Ahead ASIC Market Analysis - March 2007 Structured ASIC Market Analysis and Forecast: Opportunities Abound ASIC Market Analysis - March 2007 Programmable Logic Market Analysis & Forecast: Mid-Course Correction in Market Growth ASIC Market Analysis - February 2007 ASIC Design Starts By Key...
preview: http://www.semico.com  

conference    

IEEE International SOC Conference
Driven by the rapid growth of the Internet, communication technologies, pervasive computing, and wireless and portable consumer electronics, Systems-On-Chip (SOC) has become a dominant issue in today’s ASIC industry. SOCs have created new challenges in Design Methods, Design Tools, Design Automation, Manufacturing, Technology, and Test.
preview: http://www.ieee-socc.org   date: 9/17/2008

portal    

ChipEstimate.Com - now from Cadence
ChipEstimate.Com (now owned by Cadence) is an intuitive new tool for IC designers that generates fast and accurate chip estimates. The tool makes it easy for designers to visualize tradeoffs between key design metrics, and across technology nodes and process variants. InCyte lets users generate accurate and optimized chip estimates at the architectural stage of the design process, resulting in significantly shorter design times and lower...
preview: http://www.ChipEstimate.com  

book-classic    

ASIC Handbook, The
Handbook presenting techniques and methods that can be used to slash time to market and improve quality in ASIC development for electronics industry managers and project team members. Also covers project management and leadership components of ASIC development. DLC: Application specific integrated circuits.
preview: http://www.amazon.com   date: 5/1/2001