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eASIC and Video-Cores Deliver Low-Cost Video IP Solutions
eASIC Corporation, a provider of zero-mask charge ASIC devices, and Video-Cores, a provider of high-performance media IP cores, today announced the immediately availability of proven video IP cores for eASIC’s low-cost Nextreme ASICs.
The combination of eASIC’s technology and Video-Cores’ Core Values® video IP provides video system designers with a quick path to implementing custom functions such as video scalers, color-space converters and...
preview:
http://www.easic.com
date: 11/12/2008
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new product
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Enea OSE Real-Time Operating System Adds Multicore SMP Support ...
Enea® (Nordic Exchange/Small Cap/ENEA), a world-leading provider of network software and services, today announced version 5.4 of the Enea OSE real-time operating system.
OSE version 5.4 adds symmetric multiprocessing (SMP) support for multicore CPUs, beginning with Freescale's PowerPC-based MPC8641D and MPC8572DS processors.
Other key features include a new demand pager that supports dynamic load modules, and an enhanced IP stack with IPv6...
preview:
http://www.enea.com
date: 11/12/2008
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news release
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Denali Software Premieres Verification IP for the New SuperSpeed USB Interface
Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its PureSpec™ verification intellectual property (VIP) product now supports the USB 3.0 specification from the USB 3.0 Promoter Group , allowing device and system designers to begin advanced USB 3.0 development.
Denali’s PureSpec USB VIP product provides both design and verification engineers...
preview:
http://www.denali.com
date: 11/12/2008
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new product
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EMA TimingDesigner 9.1 Adds SDC Support and Integration with Altera’s Quartus II Software
EMA Design Automation™ (www.ema-eda.com), a full-service provider of Electronic Design Automation (EDA) solutions, today announced TimingDesigner version 9.1, adding support for SDC which provides the ability to interface with FPGA and ASIC design flows. “With TimingDesigner 9.1, EMA has taken another step in helping our customers ensure their critical interfaces are designed right the first time,” said Manny Marcano, President and CEO of...
preview:
http://www.ema-eda.com
date: 11/10/2008
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new product
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Cadence Expands Portfolio of System-Level Verification IP and SpeedBridge Adapters
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today expanded its system verification IP (VIP) and Cadence® SpeedBridge® Adapters portfolio with a focus on transaction-based acceleration (TBA) and in-circuit emulation use models.
The expanded Cadence portfolio focuses on standard protocols for the wireless, networking, storage and multimedia vertical markets, enabling system verification and...
preview:
http://www.cadence.com
date: 11/8/2008
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new product
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DFI Technical Group Releases Low Power Features with New DDR PHY Interface Specification ....
Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members, announced the availability of the preliminary version of the DFI specification 2.1. The DFI specification extends support to the latest LPDDR2 memory technology and enables new features including frequency change support and low-power PHY options.
The collaborative technical working group includes representatives from ARM, Denali, Intel,...
preview:
http://www.denali.com
date: 11/7/2008
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